Implementation of Low-Density Parity-Check (LDPC) Codes in Verilog HDL

This work presents FPGA implementation of Low-Density Parity-Check (LDPC) encoder. Low-density coding is an effective method for ensuring reliable communication over noisy channels while minimizing the probability of error. We use Verilog hardware description language (HDL) to simulate this encoder for various code rates. The encoder is implemented on the Xilinx Artix-7 FPGA(XC7A35T-ICPG236C) kit using FPGA 28 nm CMOS technology and DE10-Lite FPGA Kit using FPGA 55 nm CMOS technology.