Analysis of Multiplexer and Demultiplexer using Adiabatic Logic for low power VLSI application

With the growing demand for energy-efficient VLSI circuits, adiabatic logic has emerged as a promising alternative to conventional CMOS-based designs. This study examines the performance of multiplexer (MUX) and demultiplexer (DEMUX) circuits implemented using static CMOS, 2N2P, and 2N2N2P logic families. A comparative analysis is conducted based on power consumption, propagation delay, energy efficiency, and power-delay product (PDP). Cadence Virtuoso simulations has been used at 45nm technology. Simulation results reveal that while CMOS circuits demonstrate lower delay, they suffer from significant power dissipation, limiting their suitability for low-power applications. On the other hand, 2N2P and 2N2N2P logic-based designs effectively reduce power losses through charge recovery techniques, with 2N2P achieving superior energy efficiency. Although 2N2N2P offers a trade-off between power savings and performance, it introduces additional circuit complexity. It can be concluded that adiabatic logic provides a power-efficient alternative to traditional CMOS, making it highly suitable for low-power VLSI applications.