Design and Analysis of Current Starved Voltage Controlled Oscillators using 7nm Technology

In the field of Very-Large Scale Integration (VLSI), Oscillators play a very crucial role and hence are widely used across the globe. The designers in VLSI field use Ring Oscillators for Global Process Monitoring. These ring oscillators are better used if the frequency is controlled, making it of use with multiple frequencies. The frequency is thus controlled by delay manipulation which can be done by controlling supply voltage, load capacitance, control voltage, and effective width of device. These are applied in wafer testing to determine the impact of variations in the manufacturing process. Ring oscillators may also be utilized to determine the impact of voltage and temperature on a chip. A better frequency range makes the oscillators to be used in Integrated Circuits (ICs) to generate clock, PLL, signal generators, radios, television, and many more. This work presents the design and analysis of different designs of Current Starved Voltage Controlled Oscillators (CSVCOs). The study examines the impact of changing design parameters on performance parameters such as frequency, power consumption, and phase noise, jitter and output noise. Simulation results identify the trade-offs of each configuration, providing insights into the best design options for a variety of applications. We are using 7nm technology node to implement our designs in Cadence Virtuoso software.