Compact Modeling and Cryogenic Benchmarking of 14 nm FinFETsWith Advanced HZH Gate Stack

The continued miniaturization of Si-FETs is approaching fundamental limits, prompting the exploration of innovative enhancements to transistor functionality, novel computing paradigms, and vertical integration at the architectural level [1]. Among these, gate stack plays a pivotal role as a universal performance booster for FETs, irrespective of the channel material—be it silicon, emerging high-performance materials, or those suitable for three-dimensional integrated devices [2]. The transition from traditional SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> gate dielectric to $\mathrm{SiO}_{2} / \mathrm{high}-k$ gate stack marked a transformative milestone in computing technology. In this context, a CMOS-compatible high-k oxide/interfacial-layer (IL) stack with negative differential capacitance (NDC), which does not degrade channel transport properties, presents an exciting avenue for low-power logic technology. More importantly, recent developments suggest that 2 nm thick $\mathrm{HZH}, \mathrm{HfO}_{2}-\mathrm{ZrO}_{2}-\mathrm{HfO}_{2}(0.35-1.3-0.35 \mathrm{~nm})$, stacked with IL offers better NDC characteristics [3, 4]; hence, this can enable a better low-power logic device than other CMOS compatible NDC stacks. Here, we report the quantitative improvement in the performance at the device and circuit level comprised of 14 nm Si-FinFET, down to cryogenic temperature (CT), with HZH/IL in the gate stack.