Implementation of SEC-DED-DAEC Using Model-Sim and DE10- LITE

Error-prone data transmission processes in advanced communication systems are becoming effortless in the context of modern high-speed and long-distance networks. Single or multiple bit errors can occur, which can affect data accuracy in the system. Several error correction techniques are used to overcome this problem. Hamming codes are efficient at detecting single-bit errors but are not able to address multiple bit errors. They are used for Single Bit Error Correction and Double Error Detection (SEC-DED). As the name suggests, they only correct single-bit errors. To address this limitation, the Single Error Correction - Double Error Detection - Double Adjacent Error Correction (SEC-DED-DAEC) coding has been developed. This technique not only corrects 1-bit errors but also detects 2-bit errors and corrects 2-adjacent bit errors, thereby enhancing the reliability of modern communication systems. We conducted a simulation and validated the results using the DE10-Lite FPGA, providing a practical demonstration of its effectiveness in real-world applications. The simulation tool, ModelSim, was used to validate the encoding and decoding processes.