A 12-bit Current-Steering DAC with Output Impedance Compensation for PNN Prototyping

This article presents the design and implementation of a highly linear and output impedance compensated digital-to-analog converter (DAC). The proposed architecture minimizes layout area while maintaining high linearity and optimized output impedance. The DAC comprises several key functional blocks, including a Stacked current steering array, a Dynamic Element Matching Coder (DEM), a Splitting Decoder, a Dynamic Element Matching and Full Differential Current Return-to-Zero Logic Controller (DEMRTZ Control), a Switch Driver Array, a Bias Circuit, and an Output Impedance Compensation (OIC) module. Each component plays a crucial role in improving the overall performance of the DAC in terms of linearity and impedance characteristics. The proposed DAC is designed using TSMC TN40G process technology with a core circuit area of 242.555 × 166.2 μm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. Post-layout simulations show that at an input frequency of 0.56 MHz, the DAC achieves an ENOB of 11.68 bits and an SFDR of 84.17 dB. At 48.65 MHz, the DAC maintains an ENOB of 10.78 bits and an SFDR of 76.77 dB.