NCSSLIM: NCFET-Based Secure Light Weight SLIM Cipher Design for Energy Efficient and DPA Resistant IoT Edge Devices

With the shrinking in CMOS technology nodes and the rise in various hardware attacks, designing energy-efficient and secure light weight ciphers for resource constrained Internet of Things (IoT) edge devices has become a major challenge. This paper explores the utilization of unique steep slope characteristics of Negative Capacitance FETs (NCFETs) to create energy-efficient and light weight SLIM cipher resistant to differential power analysis (DPA) attacks at scaled supply voltages, V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf>=0.5V. At a ferro electric layer thickness, T<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fe</inf> of 3nm, NCFET based SLIM cipher design shows ~4.25× lower energy consumption due to the steep slope characteristics in comparison to the baseline 40nm CMOS SLIM cipher design at V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf>=0.5V. Due to the increased nonlinearity in power traces by the extra capacitance of the NCFET device structure, the proposed NCFET based SLIM cipher achieves ~16× increased attacker effect ratio, Signal to Noise Ratio (SNR) of ~3.7× lower, Minimum Traces to Disclosure (MTD) value of 16× higher, and the Security Power Delay (SPD) value of ~13.4× higher than the equivalent baseline CMOS SLIM S-box design with 256 power traces at V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf>=0.5V.