Low Power Current Starved VCO Design in SCL 180nm CMOS Process

A low power Voltage controlled Oscillator (VCO) is presented in this paper which is designed using current starved technique and has 5-stages. The VCO circuit is designed using SCL 180nm technology with supply voltage of 1.8V achieves a frequency of 458 MHz at the control voltage of 1.8V and implemented in Cadence virtuoso environment. The circuit achieved a power dissipation of 87.43 μW and a phase noise of -76.81 dBc/Hz at an offset of 1MHz.