FPGA-Based High-Efficiency Accelerator for UNET with Symmetric Pruning Strategy

UNET demonstrates exceptional performance in image segmentation tasks. However, its complex structure and large number of parameters pose challenges for deployment on resource-constrained devices, limiting its applicability in real-time and edge computing scenarios. To address this issue, we propose an FPGA-based acceleration solution for UNET, combining model compression and hardware optimization. First, we propose a Korder pruning method to compress the UNET model, which reduces its parameters while preserving structural symmetry, significantly lowering computational complexity with only a negligible loss in accuracy. Next, a high-parallel convolutional unit that consists of 3D DSP arrays cascaded horizontally and vertically is designed, minimizing the consumption of intermediate registers and significantly optimizing data reuse. To further enhance overall performance, a compact on-chip buffer bank is introduced into the proposed accelerator architecture. The buffer bank offers diverse storage modes to accommodate data of varying dimensions, thereby reducing reliance on off-chip memory. The proposed accelerator is implemented on the Xilinx VCU128 platform. The experimental results demonstrate that the K-order pruning achieves a compression ratio of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$12.46 \times$</tex>, while the accelerator attains an energy efficiency of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{6 7. 3 7}$</tex> GOPS/W and an operation efficiency of 0.888 ms, indicating that our design outperforms CPU, GPU, and existing solutions.