A Strong Physical Unclonable Function Using Dual Time-To-Digital Converters for Amd Fpgas

This paper presents a Strong Physical Unclonable Function (PUF) for AMD FPGAs using two identical Time-toDigital Converters (TDCs) with only Look-Up Tables (LUTs) and Flip-Flops (FFs). In normal operation mode, the proposed PUF operates as two independent single delay-line based TDCs (SLTDCs). In PUF mode, the proposed PUF utilizes the remaining resources within the implemented Configurable Logic Blocks (CLBs) to construct identical TDCs with nonuniform delay and a wide measurement range. By simultaneously inputting the same time interval multiple times to these TDCs, delay measurements are performed. The response output is generated from the average delay difference obtained from the measurement results. By inputting a large time interval to the wide measurement range TDCs, the effects of manufacturing variations of the implemented chip appear as an average delay difference. Additionally, by compensating the measurement range variations of the two TDCs, improvements in uniformity and uniqueness are achieved. Evaluation using 10 Artix-7 FPGAs resulted in an inter-chip HD of 50.94 %, an intra-chip HD of 19.11 %, and a uniformity of 49.53 %.