12-bit 100 MS/s Time-Relaxed Interleaved Randomly Selected DAC for Real-time FOG Systems

This article presents a 12-bit time-relaxed interleaved randomly selected Digital-to-Analog Converter (DAC) implemented using the TSMC TN40G process technology. The DAC operates at a clock frequency of 100 MHz with a core circuit area of 248 × 203 µm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a supply voltage of 0.9 V. The design features two sets of stacked current source arrays, arranged in a staggered manner to optimize switching performance. Simulation results demonstrate that the proposed DAC achieves an SFDR of 61.2 dB at DC (Fin = 9 MHz) and 71.9 dB near Nyquist (Fin = 49 MHz, 0.5 Fs), with a total power consumption of 26.9 mW. The proposed DAC design highlights dynamic performance, power efficiency, and mismatch error reduction, making it a promising solution for fiber optic gyroscope (FOG) systems.