Implementation of Scalable FFT Algorithm Based on Parametric Design

This paper addresses the issue of insufficient flexibility and low resource utilization in traditional fixed-point FFT processors. A configurable FFT/IFFT design is proposed, where the number of FFT computation points and the number of parallel butterfly transformations can be configured. The hardware design is implemented using Verilog, employing a time-decimation Radix-2 algorithm and parallel iterative structure, capable of processing 16-bit signed data for 8-4096 point FFT computations. VCS and Verdi were used for compilation and simulation verification, while Vivado was used for synthesis. Finally, the simulation results were compared and analyzed against theoretical results generated by MATLAB to verify the accuracy of the design. Fixed-point arithmetic is used to reduce computational complexity. The design achieves a butterfly operation in just 5 clock cycles, and with a clock frequency of 50 MHz, the 4096 -point FFT can be completed in a maximum of 1.2 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu \mathrm{s}$</tex>.