Nanowire FET Design and Analysis for Low-Power Applications
Because of their exceptional electrostatic control and scalability, nanowire field-effect transistors (FETs) have become an appropriate approach for future-oriented low-power electronic devices. The design and analysis of nanowire FETs are presented thoroughly in this paper, with an emphasis on improving device parameters for achieving excellent performance at low power usage. To improve energy efficiency, we investigate important design elements such as device scaling, gate designs, and channel materials. Additionally, the properties of nanowire FETs are examined through simulations, demonstrating their potential for ultra-low power circuits. The results show that nanowire FETs can improve switching efficiency and reduce leakage currents, making them a great choice for next-generation low-power electronic systems.
Authors
- M Uma rani
- Tarun Chaudhary (ORCID: https://orcid.org/0000-0003-1854-4535)
- Mandeep Singh (ORCID: https://orcid.org/0000-0002-4577-2675)
- Harsh Harsh
- Balwinder Raj
- P. Mittal
Institutions
- Dr. B. R. Ambedkar National Institute of Technology Jalandhar (IN)
- Indian Institute of Technology Kanpur (IN)
Publication Details
- Published
- 2025-06-05
- DOI
- https://doi.org/10.1109/eaic66483.2025.11101388
- Primary Topic
- Advancements in Semiconductor Devices and Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00