NCFET based Low Energy Overhead and Robust Logic Locking Design for Enhanced Hardware Security

Recent focus has been on creating reliable and secure hardware for Edge AI devices as Deep Learning applications continue to rise. Logic locking has emerged as a reliable technology for ensuring secure and trustworthy designs through hardware obfuscation. CMOS based logic locking methods lead to higher propagation delay and increased energy consumption due to the addition of logic gates for logic locking. In this work, a novel logic locking design with low energy consumption overhead utilizing Negative Capacitance FET (NCFET) has been proposed for hardware obfuscation in a PRIDE S-box circuit design operating at V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf>=0.5V. Our study on the NCFET PTL based PRIDE S-box locked circuit design, incorporating an optimal ferroelectric thickness (t<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fe</inf>) value to ensure a full logic swing for robust PTL design, has demonstrated a significant improvement. Results show a reduction of approximately 47.58% in area overhead and about 61.6% in energy consumption overhead.