A Low-Noise Dual-Path Digital-Assisted Phase-Locked Loop Simulink Model Design

This paper presents the model design of the dualpath digital-assisted phase-locked loop. A low noise dual-path phase-locked loop scheme with the digital time converter (DTC) compensation technology is proposed. The dual-path structure can effectively reduce the in-band phase noise and theoretically save chip area, while the DTC compensation technology can effectively suppress the quantization noise injected into the loop by the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta-\Sigma$</tex> modulator. As a result, the jitter and in-band noise of the output signal can be reduced and the performance of the phase-locked loop is improved. Based on the theoretical analysis and structure design of the dual-path DTC digital assisted phaselocked loop, this paper demonstrates the transfer function and noise model of the phase-locked loop system, and uses Simulink to model and simulate the proposed phase-locked loop. The simulation results prove the reliability and effectiveness of the proposed low noise dual-path digital assisted phase-locked loop.