Design of a Hybrid Branch Prediction Architecture for Risc-V Processors

Branch prediction is critical for performance in modern high-speed processors, whereas branch prediction error results in pipeline flush and execution stalls. This paper presents a hybrid branch prediction architecture that combines global and local history predictors to improve accuracy in a 32-bit dual-issue superscalar processor. The design integrates a global history Gshare predictor and a local two-level adaptive predictor using a tournament-style selection mechanism. We address practical implementation issues, including concurrent prediction of multiple branches per fetch bundle and a speculative update strategy for predictor state. The proposed hybrid predictor was implemented and evaluated on industry-standard benchmarks. On the CoreMark benchmark, the hybrid predictor achieves a score of 3.128 CoreMark/MHz with a MPKI(Missed Predictions per Kilo Instruction) as low as <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{1 4. 3 7 3}$</tex> and a prediction accuracy of 93.09 %, about 5 percentage points higher than a baseline bimodal predictor. These results demonstrate that combining global and local prediction techniques can significantly reduce prediction error rate and improve overall processor performance.