A Comparative Analysis of 4:1 Multiplexer Design Using 2:1 Multiplexers in Terms of Delay and Power

NAND gates, as they are implemented by 180nm, 90nm, and 45nm CMOS technologies also in SCL180, are applied in this work to construct and study a 4:1 multiplexer (MUX). each of which is built from NAND gates. The Cadence Virtuoso platform is employed to simulate the design and examine performance aspects such as power consumption and propagation delay. The aim of this research is to shed light on how NAND-based MUX designs in modern CMOS and SCL180 technology can be utilized to design logic circuits in an optimal fashion.