Towards Fast Gaussian Process Regression Models: An FPGA-based Implementation of the RBF Kernel Matrix Computation

Gaussian Process Regression (GPR) is a machine learning technique that, besides predicting certain target values, also quantifies their uncertainty. With that, GPR is increasingly gaining significance for mission-critical applications, such as in the development of virtual metrology for key processes in the semiconductor industry. However, successfully deploying these models in the industry requires real-time execution at the edge - which poses a major challenge considering GPR’s high computational complexity. Thus, we present an FPGA-based hardware accelerator design for the Kernel Matrix computation using the RBF kernel function. The accelerator is designed to be highly flexible and configurable, responding to a wide range of possible input datasets - independent of the number of samples of each input feature matrix and the number of features. This is mainly achieved by applying a Matrix Tiling technique where the input matrices are partitioned into smaller blocks that are successively loaded into the on-chip memory and reused repeatedly. Double buffering, pipelining, and burst transfers are used to further improve the data movement. Using High-level synthesis allows fast and easy adaption of the hardware design, thus considerably contributing to the accelerator’s flexibility. On the Zynq Ultrascale+ MPSoC ZCU102, the presented hardware design achieves an acceleration of more than $10 x$ compared to the according Python function that is run on the ARM processor of the MPSoC while using only up to about 20% of the hardware resources. Therefore, the proposed accelerator is an important first step towards a faster and adaptable GPR implementation. Next steps will include further optimisation and extensions of the introduced hardware design and the implementation of additional parts of the GPR algorithm.