Performance and low power optimization of two-dimensional SiC field effect transistors with asymmetric electrodes

By using the first-principles method based on density functional theory and non-equilibrium Green's function, we studied the transport properties of 5 nm two-dimensional SiC Field-effect transistors with asymmetric metal phases 1T-MoS<sub>2</sub> source and Pd drain electrodes. The influence mechanism of the increase of 1T-MoS<sub>2</sub> electrode layers and the decrease of working electrical compression on the device’s performance is systematically analyzed. The Schottky barriers extracted from the zero bias and zero gate voltage transport spectra show that the valence band maximum of SiC in the channel regions of MFET, BFET and TFET are closer to the Fermi level after the source drain electrode is balanced. Therefore, the three devices belong to P-type contact, and the hole Schottky barrier height increases with the increase of the number of 1T-MoS<sub>2</sub> layers of the source electrode, which are 0.6, 0.76 and 0.88 eV, respectively. In addition, the increase of 1T-MoS<sub>2</sub> layers will also lead to the increase of the density of states in the source electrode, thereby improving the transport coefficient at the band edge. The effect of the two on the transport capacity of the device is opposite, and there is a competitive relationship. The transfer characteristics of devices show that the wide band gap of SiC can significantly suppress the short channel effect, so that all devices can meet the requirements of off state. More importantly, the subthreshold swing of all devices at 0.64 V operating voltage is close to the physical limit of 60 mV/dec. The ON-current of MFET, BFET and TFET can reach 1553, 1601 and 1702 μA/μm under the more stringent IRDS HP standard, and the three performance parameters of intrinsic gate capacitance, power-delay product and delay time can greatly exceed the international road map of equipment and systems (IRDS) standards for high-performance devices. In addition, the working voltage of MFET can be reduced to 0.52 V, and the corresponding power-delay product and delay time are as low as 0.086 FJ/μm and 0.038 ps, which are only 14% and 4% of the IRDS standard. The asymmetric source drain electrode design strategy proposed in this work not only solves the problems of low on state current and short channel effect restricting off state current of existing two-dimensional material Field-effect transistors, but also provides an important solution for the development of ultra-low power nano electronic devices in the post Moore era.