Development of sputtering targets for TSV in 3D integrated circuits

Abstract Through silicon via (TSV) technology in three-dimensional integrated circuits can achieve interconnection through stacking chips, which is an important way to break through the limitations of advanced integrated circuit processes, improve overall chip performance, and reduce its size. This article introduces the preparation method of high-performance sputtering targets (including copper and tantalum targets) for TSV manufacturing. The uniformity of the microstructure (grain size, orientation) of the sputtering target was controlled through strict manufacturing techniques.