Selective Update for Hardware‐Friendly On‐Chip Training in Distributed Analog In‐Memory Computing Systems

Analog in‐memory computing (AiMC) significantly enhances computational efficiency for artificial neural networks by performing computations within memory. However, the implementation of convolutional neural networks in AiMC faces a bottleneck due to excessive kernel weight sharing. While data parallelism with weight replication accelerates inference by distributing computation, performance degradation caused by nonidealities in crossbar arrays necessitates on‐chip training in such systems. This study proposes a selective weight update method that accelerates training by reducing pulse generation opportunities for update to a square‐root level by defining gradient importance based on kernel mapping and implementing gradient synchronization in crossbar‐based distributed systems. The approach demonstrates robustness against memory state variations, as well as cycle‐to‐cycle and device‐to‐device variability, while minimizing write disturbance effects. The proposed method achieves >99% on‐chip training accuracy in a checkerboard image classification task using a 5×5 array of 6T1C synaptic cells composed of six IGZO thin‐film transistors and a capacitor.