A Lightweight Method for Circuit Sensitive Point Analysis of Aerospace-Grade Static RAM-Based Field-Programmable Gate Arrays

This paper presents a lightweight method for analyzing sensitive points of the Hardware Design Language (HDL)-designed circuit implemented in aerospace-grade Static RAM (SRAM)-based Field-Programmable Gate Arrays (FPGAs), which are prone to Single-Event Upsets (SEUs) due to radiation in space environments. The proposed method leverages circuit netlists and layout information to model the FPGA circuit as a directed graph, where instances are nodes and nets are edges. Two algorithms are introduced: one identifies the longest forward propagation paths, and the other determines nodes with the maximum downstream connectivity. These algorithms efficiently pinpoint critical nodes that are more likely to cause circuit errors when affected by SEUs. The method is validated through fault injection experiments on Xilinx VU3P FPGAs, demonstrating that the identified sensitive nodes have a significantly higher fault frequency compared to randomly selected nodes. The results confirm the accuracy and effectiveness of the proposed approach, offering a rapid and reliable way to detect and mitigate soft errors in aerospace applications. This advancement is crucial for enhancing the reliability of FPGA-based systems in radiation-prone environments.