Advanced Interconnect Technologies for SRAM Design: Evaluating Energy Efficiency and Performance at the 7nm CMOS Technology Node

This work introduces a comprehensive design framework for SRAM systems at the 7nm node, integrating advanced nanoscale interconnect options to enhance performance and energy efficiency. The SRAM system design framework supports scalable memory configurations through a streamlined workflow that includes RTL design, synthesis, floor planning, place-and-route, and clock tree synthesis. We conduct a detailed comparison of interconnect technologies-Copper BKM (industry best-known method), CuThin, Improved Via, and Ruthenium-revealing significant performance differences. Ruthenium-based interconnects demonstrate superior energy efficiency, reducing energy-delay product (EDP) and leakage power significantly while maintaining a compact area. Specifically, for 1MB SRAM, Ruthenium interconnects achieve a 33.4% EDP reduction and a 20.4%increase in effective frequency compared to CuBKM. It is also noticed that only improving the via resistances can reduce the EDP by 16.6% from CuBKM. These results highlight the potential of Ruthenium and Improved Via as promising interconnect solutions for high-performance, energy-efficient SRAM design in advanced technology nodes.