Design of Static Single-Phase Flip-Flops for Energy-Efficient Near-Threshold Voltage Operation

Flip-flops (FFs) and clock distribution networks, two core parts of the clocking system, are becoming increasingly important in chip design. They consume 60% of the overall dynamic power because of the constant clock transition and a large number of clock transistors in each FF. FFs and latches dissipate 50% of the overall dynamic power. They also have a significant impact on the performance, robustness, and size of the circuit in the near-threshold voltage (NTV) region. Thus, static and energy-efficient FFs are required in sequential circuits for NTV operation. In this paper, we propose two static contention-free single-phase negative edge-triggered flip-flops: a Low Transistor Count FF (LTCFF) and an Ultra-Low Power FF (ULPFF). Both designs reduce the number of clock transistors to just four. In the LTCFF, the transistor count is reduced to 16 by using a merging and sharing approach, while the static behavior of the FF is kept. The ULPFF, consisting of only 22 transistors, is extended from the LTCFF by eliminating redundant internal transitions to ensure ultra-low power operation. Designed in a 65-nm technology using Cadence Virtuoso, the proposed LTCFF and ULPFF achieve a reduction of 68.77% (or 67.05%) and 74.22% (or 70.58%) in the power-delay product (PDP), compared to the widely used transmission gate flip-flop (TGFF) at a supply voltage of 1 V and 1 GHz clock frequency (or 0.4 V and 25 MHz) with 10% data activity. These designs are simulated with different voltages from 0.4 V to 1 V and process corners to ensure good performance in near-threshold operation and that there are no floating nodes for any input combination.