A 40-Nm Cmos 12-B 500Ms/S Pipelined Adc With Digital Calibration

This paper proposes a digital calibration method for correcting capacitor mismatches and gain errors in pipelined stages. The effects caused by non-ideal factors are calibrated in the foreground and background. A <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$500-\text{MS} / \mathrm{s}$</tex> pipelined analog-todigital converter (ADC) is designed in <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$40-\text{nm} 1.1-\mathrm{V}$</tex> CMOS technology. For a 74.83 MHz sinusoidal signal, the calibration technique achieves a signal-to-noise-distortion ratio (SNDR) of 63.14 dB and a spurious-free dynamic (SFDR) of 75.14 dB, respectively. The ADC consumes 73 mW and has <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{0. 1 3 6 - p J}$</tex> /step figure of merit (FoM).