A Test Vector Retargeting Circuit for Chiplet Stacking Structure

With the limits of Moore's Law approaching, the traditional semiconductor industry is shifting from single-chip integration to multi-chip heterogeneous packaging integration technologies. Chiplet stacking technology is expected to become the mainstream technology for future chips. To address the testing challenges associated with multi-chip stacking, this paper proposes a 3D testability design circuit structure for chiplet stacking systems, based on the IEEE 1500 and 1687 test protocols and automatic chiplet detection mechanisms. The proposed test circuit extends the traditional test access port (TAP) controller by adding more test instructions, thereby enriching the test modes. It uses upper and lower chiplet detectors to automatically configure the test path between pads and TSVs, enabling test instruction retargeting for memory built-in self test (BIST) at the bottom chiplet's pad ports and internal cores test retargeting for other layers of chiplets. Simulation results show that the proposed test circuit can perform embedded instrumentation tests for chiplets at different levels, applicable to various binding levels of vertical stacking without configuration steps, and the number of external test ports is only five from the bottom chiplet.