Edge Computing for Sports Motion Detection Using a High-Efficiency FFT Processor

With the advancement of edge devices, their application in sports motion detection has become increasingly prevalent. However, their widespread adoption remains limited due to high computational complexity, power consumption, and implementation costs. In this paper, we propose a specialized edge computing system tailored for the enhancement and detection of moving objects in motion imagery. Specifically, we introduce a highly optimized FFT module designed explicitly for hardware-friendly implementation. We present a hardware-efficient Mixed Radix Multipath Delay Feedback (MRMDF) FFT processor capable of supporting radix-2, 3, 5, and 11 FFT computations. A parallel architecture in the first stage significantly simplifies complex twiddle factor multiplications through Canonical Signed Digit (CSD) constant multiplications, dramatically reducing computational complexity. To accommodate varying FFT lengths efficiently, multiple parallel Single Delay Feedback (SDF) stages are adopted in the subsequent processing stage. In particular, an optimized 11-point FFT structure based on SDF architecture is developed using folding and register minimization techniques. Fabricated using a 55-nm CMOS technology, the proposed FFT processor achieves a throughput of 16.064 GW/s at an operational frequency of 502 MHz, with a normalized hardware efficiency of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.68 \text{GW}/\mathrm{s}/\text{mm}^{2}$</tex>. Experimental results demonstrate the efficacy of our system through successful application in real-time tennis motion detection scenarios.