Quantum Confinement Effects on Carrier Distribution in Nanoscale HFET, Si MOSFETs and SOI Devices: 1D Poisson-Shrödinger Solver

This study investigates the impact of quantum confinement effects on carrier distribution in nanoscale HFETs, SOI devices, and MOSFETs. As semiconductor dimensions shrink to the nanometer regime, traditional classical models fail to accurately describe carrier behavior due to pronounced quantum effects. To address this challenge, a 1D Poisson-Schrödinger solver is employed to simulate carrier distributions under quantum mechanical frameworks. This study calculates the polarization charge densities at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{GaN} / \text{In}_{0.2} \text{Ga}_{0.8} \mathrm{N}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{Al}_{0.3} \text{Ga}_{0.7} \mathrm{N} / \text{GaN}$</tex> heterojunctions and simulates the 2DEG distribution in HFETs under varying gate biases. Results show that quantum confinement significantly affects 2DEG distribution, and differences in polarization charge due to material systems significantly influence the device turn-off voltage. In SOI and Si-MOSFETs, quantum effects modify the conduction band profile and electron density distribution. The study highlights that quantum confinement reduces peak electron density near the interface while shifting its position deeper into the potential well, challenging classical assumptions of thermal equilibrium. This work provides critical insights for designing nanoscale devices, emphasizing the importance of band engineering and material selection to mitigate parasitic effects and optimize quantum confinement benefits. The findings advance the development of high-performance nano-electronics by bridging quantum mechanical simulations with practical device architectures.