Design and Analysis of Nikhilam based Vedic Architecture for High Speed Arithmetic Operations on FPGA

Objectives: With rising computational demands in signal processing and machine learning, achieving high-throughput and low-latency multiplication on FPGA platforms is critical. This work targets the design, implementation, and synthesis results of 2-bit, 22-bit, 23-bit, 24-bit, and 25-bit binary multipliers using the Nikhilam Sutra of Early Indian Vedic Mathematics are explored in this paper. Methods: This study implements 2-bit, 22-bit, 23-bit, 24-bit, and 25-bit binary multipliers using VHDL Coding with reusable components such as AND gates, 2:2, 3:2 compressors and sub-multipliers. Findings: The coded design is implemented using Xilinx ISE 14.7 targeting spartan-3E FPGA, and afterwards performance matrices including utilization of RAM space, delay, LUTs & Level of Logic are compared across bit-width 2, 2^2, 2^3, 2^4 and 2^5. Novelty: By extending the design to 32 bits and systematically comparing resource tradeoffs, this study provides comprehensive insights into Nikhilam-sutra results of simulation and synthesis approve that the proposed Nikhilam-based multipliers are precise, scalable, and offer a balanced trade-off between speed and hardware complications, making them suitable for FPGA-based performance-critical applications. Keywords: Adder, Multiplier, FPGA, Compressors, Response time, Nikhilam Sutra