Low Power 8T and 9T SRAM Cell Configurations using Improved SVL (I-SVL)

Background/Objectives: Memory is important in today's world of electronic equipment, such as processors and portable electronics, thanks to the use of static random-access memory (SRAM). Low-power electronic devices, such as PDAs and cell phones, are the goal of the current generation. Consequently, the design of low power SRAM has a vast array of uses. However, the SRAM design adds a higher power requirement. Therefore, there is still opportunity to develop an appropriate low-power memory cell. The implementation of low power reduction solutions satisfies this urgent demand. Additionally, these devices require cache memories, which are created using Static Random Access Memory cells (SRAMs). Using power reduction strategies to create SRAM cells with low leakage is now a difficulty. Methods: In the present context the designing and implementation of low power 8T and 9T SRAM cells has been carried using SVL and I-SVL techniques for various process corner models. The simulation has been carried using Microwind DSCH (version 3.5) and all simulations are carried out using Microwind version 3.1 with 90 nm technology library at 1.2 V of Vdd. Findings: The proposed 8T I-SVL based cells shows improvements in power by 18% and 69% using BSIM 4 in comparison with the Level 3 and Level 1 models respectively. The proposed 9T I-SVL based cells shows improvements in power by 30% and 1.8% using Level 3 in comparison with the Level 1 and BSIM 4 models respectively. Novelty: This study proposes Low power 8T and 9T based SRAM cells in terms of static and dynamic power in comparison with the existing literatures through the usage of I-SVL techniques. In addition, the proposed I-SVL 8T and 9T SRAM cell shows 52% and 68% improvements in terms of total power comparatively with the existing works. Keywords: SRAM, Improved – Self Controllable Voltage level (I-SVL), Improved lower SVL (I-LSVL), Improved upper SVL (I-USVL), Self Controllable Voltage level (SVL)