A 11T SRAM Circuit Design with Ultra-Low-Voltage for High-Stability Applications

This paper proposes an 11T SRAM cell for sub-threshold operations in 130nm CMOS technology, addressing stability and leakage challenges in low-voltage regimes. By decoupling read/write ports and optimizing transistor sizing, the design eliminates half-select issues and reduces leakage by 2.17× compared to 6T SRAM. Post-layout simulations demonstrate 295 kHz operation at 0.35 V with 0.88×read stability improvement over 8T cells, achieving 1.2 pJ/cycle energy efficiency.