Efficient Convolution Accelerator Using Number-Theoretic Transform for Deep Learning on Fpga

With the wide application of deep learning technologies in edge computing and IoT devices, low-power and highefficiency convolutional operation acceleration has become a key requirement. Traditional direct convolution has high complexity, while convolutional operations relying on Fast Fourier Transform (FFT) suffer from loss of floating-point accuracy and large hardware resource consumption. In this paper, we propose an efficient and configurable convolution accelerator design based on the number-theoretic transform (NTT) and implement it on FPGA. The proposed method maps convolution computation into the integer domain, leveraging NTT modular arithmetic and the parallel butterfly structures, achieving high-precision integer convolution with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$O(N \log N)$</tex> complexity. The design adopts a parameterized architecture and supports dynamic configuration of input data length (16-256) and bit width (8 / 16 / 32 bits). It achieves efficient processing by Barrett's modulo approximation and subtraction algorithm and butterfly operation. Experiments show that on the Xilinx ZedBoard platform, the accelerator achieves a speedup of up to 344 times compared to the CPU, with a dynamic power consumption of only 0.401 W and a favorable trade-off between resource utilization and performance. This study provides a new hardware acceleration scheme for deploying convolutional neural networks on edge devices, which is valuable for improving the efficiency of deep learning inference.