Hardware Acceleration of LDPC Encoding Based on CGRA

Low-Density Parity-Check (LDPC) codes, as a class of capacity-approaching forward error correction codes, have been adopted as the encoding strategy for 5 G New Radio data channels. With the exponential increase in data throughput requirements for 5G communications, conventional FPGA-based architectures have demonstrated notable limitations in terms of computational efficiency and scalability. This paper introduces CGRA as a hardware acceleration approach for LDPC encoding. To address the issues of low memory utilization and low computing efficiency in CGRA, we employ data preprocessing, heterogenous memory architecture, and optimized dataflow to enhance hardware acceleration performance. Experimental results based on a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$5 \times 5$</tex> Processing Element Array (PEA) demonstrate that our approaches achieve significant performance improvements, including 80 % reduction in data access latency and 43 % decrease in computational processing time compared to baseline implementations.