A Hardware-Software Co-Design FPGA Acceleration Platform for Driver Behavior Recognition Based on MobileNetV2

Driver behavior recognition has become a critical issue in the field of intelligent transportation systems. However, traditional CPU or GPU based recognition systems often suffer from high power consumption and large computational overhead, making them unsuitable for realtime embedded applications. To address these challenges, this paper proposes a hardware-software co-design acceleration platform based on FPGA for dangerous driving behavior recognition, leveraging the lightweight MobileNetV2 model. Key optimization techniques, including operator fusion, fixed-point quantization, array partitioning, and loop unrolling, are applied to enhance computational efficiency and reduce memory bottlenecks. The platform is implemented on the PYNQ-Z2 development board, with critical computation modules such as convolution and depthwise separable convolution designed as hardware IP cores. Experimental results demonstrate that the proposed system reduces inference latency by approximately 21 times compared to a pure ARM-based implementation, while maintaining high recognition accuracy. This work highlights the potential of FPGA-based solutions for energy-efficient and real-time driver behavior recognition in embedded environments.