Optimizing WCET Analysis on Timing-Anomaly-Free Architectures

Worst-case execution time (WCET) analysis in real-time systems is challenging on modern processors due to timing anomalies - situations where locally faster operations can paradoxically lead to longer overall execution times. Traditional WCET analysis must safely explore numerous hardware states to cover such non-monotonic behaviors, causing state-space explosion and pessimistic bounds. In this paper, we leverage timing-anomaly-free processor architectures to optimize WCET analysis. We focus on processors that is free from timing anomalies, which allows the analysis to search only the local worst-case execution paths without missing the global worst case. Our method avoids exhaustive state enumeration within basic blocks, instead, it analyzes only the single local worst-case execution per block, resulting an massive reduction in analysis complexity. Finally, we report experimental results on benchmark programs showing that our optimized WCET analysis is faster than traditional method by a factor of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{4. 2 4}$</tex> approximately, these results demonstrate a practical path to fast and precise WCET analysis by co-designing timing-predictable architectures and analysis methods.