Analysis of Surface Orientation and Channel Direction in GAA Nanosheet FETs for CMOS Logic Performance

This study examines the impact of different surface orientation and channel direction combinations on the electrical performance of Gate-All-Around Nanosheet (GAANS) FETs, to optimize the logic operation. The surface orientations (100) and (110) are considered, and for each surface orientation, two channel directions, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&lt; 100 {&gt;}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&lt; 110 {&gt;}$</tex>, are investigated. When the surface orientation for <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&lt; 110 {&gt;}$</tex> channel direction is changed from (100) to (110), the p-type GAA-NS FET experiences a 25.3 % increase in drain current. In contrast, the n-type GAA-NS FET exhibits a 12.9 % reduction in drain current. Despite this, the overall performance of the CMOS inverter is enhanced. This work is based on precise device models and well calibrated TCAD simulations with experimental data. The (100)/ surface orientation/channel direction combination yields the best performance for n-type GAA-NS FET, while the (110)/ combination is optimal for p-type GAA-NS FET. Additionally, a hetero-oriented CMOS inverter, utilizing the (100)/ ntype GAA-NS and (110)/ p-type GAA-NS configurations, demonstrates the shortest rise and fall times, indicating superior dynamic performance.