Efficient FPGA-Based Implementation of Quantum Key Distribution Post-Processing System

Quantum key distribution (QKD), based on quantum mechanics, enables unconditionally secure key exchange even against adversaries with unlimited computing power. As the core of QKD post-processing, information reconciliation (IR) and privacy amplification (PA) ensure key consistency and security by correcting errors and removing leaked information. With the trend toward miniaturized and chip-based QKD systems, post-processing modules require highly integrated designs. FPGAs offer an ideal solution due to their low cost, power efficiency, and flexibility. This paper presents an FPGA-based QKD post-processing architecture using a polar codes-based appending IR algorithm, achieving reconciliation efficiency better than 1.1 under E<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">µ</inf> ≥ 0.06 and R<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</inf> = 4. A convolution-structured Toeplitz hash module is developed for PA, supporting 53.13 Mbps data rate and 26.45 Mbps key rate with R<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PA</inf> = 0.5. The complete system is implemented on a Xilinx XCKU040 FPGA. Experimental results show support for 176.58 Mbps input, 36.59 Mbps real-time processing, and 17.56 Mbps key output, demonstrating strong performance and engineering suitability. The design features high integration and portability, offering a practical hardware solution for efficient QKD post-processing.