High-Speed Signal Simulation and Optimization Based on DDR5
The continuous development of information technology has ushered in a period of high-speed development of the memory market, with the continuous improvement of CPU performance, people's requirements for memory have gradually risen. On the basis of the first generation SDRAM, DDR SDRAM was gradually upgraded and developed. Although DDR5 has advantages that DDR4 cannot match, the transmission rate of DDR5 has become faster and the bandwidth has been increased, which makes the problem of high-speed signal integrity difficult to solve. Based on the DDR5 protocol, this paper builds a model of microstrip line, stripline and via, and investigates the signal integrity of DDR5 by changing different length and dielectric constants of transmission line, length of via stub, and number of layer change, which provides a reference to the application of DDR5 in the field of microelectronics.
Authors
- Xiaofeng Zou (ORCID: https://orcid.org/0000-0002-5823-6345)
- Yongzheng Zhan (ORCID: https://orcid.org/0000-0002-1885-5950)
- Lu Zhang (ORCID: https://orcid.org/0000-0002-5779-1451)
- Yang Li (ORCID: https://orcid.org/0009-0007-4178-8446)
- Hongyang Wei (ORCID: https://orcid.org/0009-0007-7184-6264)
- Tuo Li (ORCID: https://orcid.org/0000-0002-1483-0465)
- Menglong Wang (ORCID: https://orcid.org/0000-0001-9112-4700)
- Zhenlei Zhang (ORCID: https://orcid.org/0000-0001-7776-5800)
- Qing Zhang (ORCID: https://orcid.org/0009-0000-8310-5382)
Institutions
- Shandong University (CN)
- Cloud Computing Center (CN)
Publication Details
- Published
- 2025-05-17
- DOI
- https://doi.org/10.1109/icet64964.2025.11103147
- Primary Topic
- Embedded Systems and FPGA Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00