An Analytical I-V model for GAA Junctionless MOSFETs Including Interface Trap Charges

In this paper, we present an analytical current-voltage (I-V) model for long-channel gate-all-around junctionless transistors (GAA JLTs) that incorporates interface trap charges, derived by solving the Poisson equation using the superposition method and the Lambert function. The results demonstrate strong agreement with both TCAD simulations and experimental data. This developed model offers valuable tools for studying working mechanisms, optimizing structures, and conducting circuit simulations.