A Complexity Reduced VMbPWM-Based All-Digital Transmitter With Multi-Bit Deduction Toward Higher In-Band SNR

By utilizing the mapping-based pulse width modulation (MPWM), the look-up-table (LUT) based all digital transmitter (ADT) features a superb in-band signal-to-noise ratio (SNR), but its rather high random-access memory (RAM) consumption and the computation complexity hinder its further usage in applications requiring real-time reconfigurability. Our previous work leverages a Viterbi-based PWM (VbPWM) scheme to provide an iterative deduction approach, but the degraded performance and the excessive register usage make it unsuitable for real applications. By exploring the quais-periodicity inside the differenced target function, a Viterbi-based multi-bit deduction PWM (VMbPWM) is proposed in this paper, which leverages the periodic-like feature of the target function to form a multiple-bit deduction process of the 1-bit pulse sequence. Numerical simulations suggest that the proposed scheme outperforms the MPWM by a maximum of 19 dB in in-band SNR when deducing 8 bits in a single iteration, and a maximum of 10 dB increase in SNR is presented for the VMbPWM over VbPWM when the two possess the same computation complexity. After combining iterations that deduce different amounts of bits, the computation complexity of VMbPWM can be reduced to nearly 1/4 of that when deducing 8 bits in each iteration at the cost of a 5 dB SNR degradation. Accordingly, a fully pipelined ADT structure is conducted based on the VMbPWM and is implemented with the ZCU102 evaluation kit. As depicted by the implementation results, the proposed VMbPWM-based ADT reduces the RAM usage to two tiles while eliminating the register usage from 22% using VbPWM to 15% using VMbPWM. Moreover, a reduced error vector magnitude (EVM) is demonstrated for the VMbPWM, where the maximum EVM turns out to be 2.6%, 4.0%, and 4.9% under the symbol rate of 5 MBaud, 25 MBaud, and 50 MBaud using 64QAM, which is typically 0.1%-0.2% lower than the VbPWM.