FeSATLock: An Energy Efficient and SAT Attack Resilient Logic Locking Design With FeFET LUT Architecture for Enhanced Hardware Security

Boolean satisfiability (SAT) attacks have been proven to be highly effective against logic locking techniques that secure intellectual property (IP). Prior research has improved the output corruptibility and SAT attack resiliency of logic locking, but often results in large overheads, higher design effort, increased delay and area/energy consumption. This work presents FeSATLock- a novel ferroelectric FET (FeFET) lookup table (LUT) based energy efficient and secure logic locking technique exploring the FeFET tunable device characteristics leading to both steep-slope characteristics for energy efficient circuit design and hysteresis behavior for non-volatile (NV) memory design. A FeFET LUT based key gate architecture has been proposed for key management and obfuscating the original circuit. A complete logic locking framework is demonstrated utilizing the proposed FeFET LUT based key gates, and performance has been benchmarked with baseline 40nm Complementary Metal Oxide Semiconductor Static Random Access Memory (CMOS SRAM) LUT based design at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm{V}}_{\mathbf {DD}} =0.5$ </tex-math></inline-formula>V. Due to the steep slope characteristics, at an optimal ferroelectric layer thickness (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm{t}}_{\mathbf {fe}}$ </tex-math></inline-formula>), FeFET LUT key gate design achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 2.68\times $ </tex-math></inline-formula> lower energy consumption, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 6.01\times $ </tex-math></inline-formula> higher speed with ~23% reduction in transistor count, compared to the baseline CMOS SRAM based key gate designs. The proposed FeFET LUT based locked circuit with key gates demonstrate <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 2.21\times $ </tex-math></inline-formula> reduction in energy consumption and ~4.75x improvement in circuit speed in comparison to baseline CMOS SRAM based locked designs. The proposed logic locking design methodology is further evaluated against SAT attack, robustness is compared with the existing XOR, MUX based techniques and demonstrate higher SAT attack resiliency.