Design of a segmented current steering digital to analog converter using PMOS cascode current source in UMC 65 nm technology

Digital to analog converters (DAC) are the fundamental data converters used in the digital data transmission. In this paper 8-bit DAC is proposed using current cells with LSB current of 2 µA and full-scale voltage of 420 mV. Current cells mean the current sources designed using the MOSFETs. When it comes to mixed-signal and analog integrated circuits, current cells are the fundamental building blocks that are available. The optimized performance of current source is obtained with the proper biasing circuit. The performance of these current mirrors is evaluated in terms of key parameters such as output impedance, transconductance and linearity. The simulations for testing these parameters are performed using Virtuoso Cadence tool in umc 65 nm technology. After transistor characterization, various types of current sources are designed, and for each current mirror, PVT analysis is carried out for comparison and Monte-Carlo analysis is carried out to find the mismatch in current mirrors. Then different digital blocks are designed, that are D-Latch, Binary-thermo decoder and Row-column decoder which are required for designing of current steering DAC. Creating an 8-bit segmented current steering DAC by combining the ideas of 4-bit unary weighted and 4-bit binary-weighted DACs is the aim of this research. Performance measurements such as signal-to-noise ratio (SNR), effective number of bits (ENOB), spurious-free dynamic range (SFDR), differential non-linearity (DNL), and integral non-linearity (INL) are calculated to assess the proposed 8-bit segmented DAC. The analysis and designing of current mirrors in advanced CMOS technologies are critical for the development of high performance integrated circuits. An 8-bit DAC implemented using ILSB current of 2 µA with an accuracy of ±2%.