Wirelength estimation for VLSI cell placement using hybrid statistical learning

Optimizing wirelength involves predicting the total length of wires needed to connect different components within a chip during cell placement. It is a fundamental challenge in very-large-scale integration (VLSI) of integrated circuit (IC) design, as it directly impacts the overall performance and manufacturability of chips. Accurate wire-length estimation in the early stages of the design process is critical for guiding subsequent optimization tasks. This paper proposes a novel hybrid linear regression wirelength (hybrid-LRWL) method that combines the strengths of existing methods rectilinear Steiner minimal tree (RSMT) for low-degree nets and a statistical learning-based approach for high-degree nets. Additionally, it compares the performance of three well-established wirelength estimation techniques: half-perimeter wirelength (HPWL), rectilinear minimum spanning tree (RMST), and RSMT. The methods were evaluated using the International Symposium on Physical Design (ISPD) 2011 benchmark suite, considering accuracy and computational efficiency. The experimental results demonstrated that the proposed hybrid method achieves superior accuracy, with a mean error of less than 0.05% in total wirelength, closely approximating RSMT results. The proposed method reduces computational time up to 3.6 times faster than traditional RSM-based methods. The results establish a strong framework for accurate and efficient wirelength estimation in VLSI design for modern, high-performance ICs.