Design and Analysis of Phase Locked Loop VLSI IC for Carrier Synchronization in Wireless Communications using 45nm Technology

Carrier synchronization between transmitter and receiver is essential in wireless communication. Phase locked loop (PLL) is the basic building block in the receiver to provide synchronization between transmitter and receiver in wireless communications. This Paper will be focusing on developing a specific PLL circuit for VLSI integration, which targets high frequency applications in the area of wireless communication. Owing to the use of 45 nm CMOS technology, the architecture incorporates Phase Frequency Detector and low noise VCO in order to improve performance in tuning range. Detailed simulations have shown the improvements on the performance by enhancement of the tuning range and Phase noise. This work has offered several strategies that explore the PLL design criteria, and provides a platform in terms of research for the 5G and next generation high frequency VLSI circuits within the context of wireless communication technology domain.