Improvement of conversion cycle and estimation of capacitor mismatch in hybrid analog-to-digital converters using flash and successive approximation register

Abstract This paper presents hybrid 8-bit analog-to-digital converter (ADC) architectures that consists of flash ADC and successive approximation register (SAR) ADC. We have proposed the hybrid flash-SAR ADC consisting of 4-bit flash ADC and 3-trit radix-3 SAR ADC to improve conversion speed. It is called flash-radix-3-SAR ADC. The proposed ADC consists of the 3-bit flash ADC, 1-trit radix-3 SAR ADC and 4-bit two-bit/cycle SAR ADC to reduce the number of bit in the flash ADC. It is called flash-hybrid-SAR ADC. The proposed flash-hybrid-SAR ADC can reduce by half the number of resistors and comparators in the flash ADC from the conventional 8-bit hybrid flash-radix-3-SAR ADC with the same sampling rate at 142.8 MS/s. The proposed circuit is validated through transient simulations and capacitor mismatch analysis. The results confirm 8-bit resolution with DNL (Differential non-linearity) and INL (Integral non-linearity) within ±1.0 LSB and ±0.5 LSB, respectively. The circuits also maintain stable performance under ±0.5% capacitor mismatch conditions.