A Compact 8.2 mW Complementary Current-Reusing D-Band Frequency Quadrupler in 22 nm FDSOI CMOS

This paper presents a complementary current-reusing (CCR) quadrupler in the D-band frequency range realized in a 22 nm FDSOI CMOS technology operating at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$144-169 \text{GHz}$</tex>. The circuit is based on the CCR push-push frequency doubler (CCR-PPFD) without the use of a subsequent output power amplifier (PA). By developing an analytical design flow, the transistor sizes were optimized to achieve a high total power efficiency <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\eta_{\text {tot }}$</tex> of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{2. 4 \%}$</tex> and a DC power consumption of only 8.2 mW. The occupied active area excluding pads is <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.046 ~\text{mm}^{2}$</tex>. To the best of the authors' knowledge this is the first frequency quadrupler reporting a PMOS/NMOS current reusing multiplier stage operating at D -band frequencies.