A 16-Way 115-129 GHz High Power Amplifier with 20.9 dBm $\mathrm{P}_{\text{SAT }}$ and 17.6 dBm $\mathrm{P}_{1 \text{dB}}$ in 40 Nm Bulk CMOS

This paper presents a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$115-129 \text{GHz}$</tex> power amplifier (PA) with a record <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$P_{\text{SAT }}$</tex> in <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$40-\text{nm}$</tex> bulk CMOS. The PA is based on a 4-stage differential common-source with cross-coupled capacitive neutralization with optimum device sizing and stage scaling with a transmission-line based low-loss 8:1 power combiner. On-wafer measurement shows 21.3 dB peak <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$S_{21}$</tex> and 14 GHz 3-dB bandwidth, with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$20.9 \text{dBm} P_{\text{SAT }}, 17.6 \text{dBm} P_{1 \text{dB}}$</tex> and 7.6% power-added efficiency at 125 GHz at 1.2 V supply. The chip size of the PA is <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.34 \text{mm}^{2}$</tex> including pads, with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.69 \text{mm}^{2}$</tex> core area. To the best of authors' knowledge, the proposed PA shows the highest <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$P_{\text{SAT }}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$P_{1 \text{dB}}$</tex> for a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$D$</tex>-band PA in CMOS.