Modeling of Small Source/Drain Defect in FinFET for Cell-Aware Test

In this work, Technology Computer-Aided Design (TCAD) simulations are employed to characterize the electrical behavior of source/drain (S/D) small/missing defects of FinFET, and then the corresponding SPICE model parameters are extracted to establish fault device model for circuit-level simulation. To accomplish this, a novel parameter extraction methodology, which considers the physical interpretability, is proposed. Our method enables rapid assessment of the degree of defect in terms of both physical implications (e.g., carrier transport degradation) and transistor-level electrical performance (e.g., threshold voltage shift), thereby facilitating defect-aware circuit-level fault simulation. The simulation results show that the SPICE parameters change monotonically with the degree of physical defects, leading to intermediate faulty behavior.