A Differential Rectifier Design Based on Impedance Splitting and Compression Technique for Achieving > 70% η_RF-DC Over 13 DBM Input Dynamic Power Range

This work proposes the design of a differential rectifier architecture using a novel impedance splitting technique (IST) to achieve a high power conversion efficiency (PCE) performance over a wide dynamic input power range. The technique involves splitting the input impedance into two quasi-symmetrical high and low impedance rectifier branches such that the impedance profiles of the two branches vary inversely with each other across a wide range of input power. The splitting of the input impedances into the low and high power branches are deliberately modified so that the input power can be automatically distributed between the two rectifier branches. The impedances of the individual branches are then compressed using an impedance compression technique (ICT) to minimize the impedance variation across the low and high input power range in each branch to generate a high PCE over a wide input power range. For experimental validation, the proposed rectifier design is fabricated and characterized at 4 GHz. Measurement results show the proposed rectifier is able to achieve > 60% PCE performance over a wide input power range of 17 dBm from 6 to 23 dBm, and a 13 dBm input power range from 9 d B m to 22 dBm is achieved for which the PCE is > 70%.