A Computing-in-Memory Proposal for STT-MRAM Based on PhaseFET Device Detection

Computing-In-Memory (CIM) accelerators are characterized by the integration of storage and computing functions. High-speed Magnetic Random-Access Memory (MRAM)-based CIM systems, in particular, offer a promising solution to the "memory wall" problem encountered by power-sensitive artificial intelligence edge devices. However, limitations such as a low Tunneling Magnetoresistance Ratio (TMR) and the influence of Process, Temperature, and Voltage (PVT) variations restrict the computational parallelism and accuracy of MRAM-CIM macros.To address these challenges, we propose a novel technique aimed at optimizing the row parallel computing performance of Spin-Transfer Torque (STT) MRAM-CIM. This technique integrates Phase Change Field-Effect Transistors (PhaseFETs) with Magnetic Tunnel Junctions (MTJs), significantly enhancing the TMR of storage cells. Additionally, by leveraging the rapid phase transition properties of phase change materials and implementing real-time device detection methods, we can continuously monitor the status of storage cells, enabling dynamic adjustments that support a current-domain in-memory computing scheme with improved linearity. This approach provides an MRAM-CIM solution with an area/cell of 0.4029 um<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /bitcell and a peak energy efficiency of 49.79 TOPS/W.